Fichiers concernant le boitier électrique du vhéliotech (configuration intégrale)
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2021 lines
136 KiB

(kicad_pcb (version 20211014) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
(53 "User.4" user)
(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
)
(setup
6 days ago
(stackup
(layer "F.SilkS" (type "Top Silk Screen"))
(layer "F.Paste" (type "Top Solder Paste"))
(layer "F.Mask" (type "Top Solder Mask") (thickness 0.01))
(layer "F.Cu" (type "copper") (thickness 0.035))
(layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
(layer "B.Cu" (type "copper") (thickness 0.035))
(layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01))
(layer "B.Paste" (type "Bottom Solder Paste"))
(layer "B.SilkS" (type "Bottom Silk Screen"))
(copper_finish "None")
(dielectric_constraints no)
)
(pad_to_mask_clearance 0)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(svguseinch false)
(svgprecision 6)
(excludeedgelayer true)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
6 days ago
(net 1 "Net-(J16-Pad3)")
(net 2 "GND1")
(net 3 "Net-(J12-Pad1)")
(net 4 "Net-(J12-Pad2)")
(net 5 "Net-(J1-Pad1)")
(net 6 "Net-(J2-Pad1)")
(net 7 "GND")
(net 8 "Net-(F1-Pad2)")
(net 9 "Net-(F2-Pad1)")
(net 10 "Net-(F3-Pad1)")
(net 11 "Net-(J11-Pad1)")
(net 12 "Net-(J11-Pad2)")
(net 13 "unconnected-(J7-Pad1)")
(net 14 "Net-(J10-Pad2)")
(net 15 "Net-(J13-Pad3)")
(net 16 "unconnected-(J10-Pad1)")
(net 17 "Net-(J10-Pad3)")
(net 18 "Net-(J13-Pad1)")
(net 19 "unconnected-(J17-Pad4)")
(net 20 "/5V_5A")
6 days ago
(footprint "circuit:Littelfuse_FuseHolder_FL1_178.6764.0001" (layer "F.Cu")
(tedit 6776A2CF) (tstamp 1f76df3e-c1f0-43d7-8cb2-751c4a194e12)
6 days ago
(at 110 77 -90)
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6 days ago
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(attr through_hole)
6 days ago
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(pad "1" thru_hole circle (at -4 0 270) (size 1.5 1.5) (drill 0.75) (layers *.Cu *.Mask)
6 days ago
(net 9 "Net-(F2-Pad1)") (pintype "power_out") (tstamp 63852b17-540a-42ac-851c-cf1454d083de))
6 days ago
(pad "2" thru_hole circle (at 4 0 270) (size 1.5 1.5) (drill 0.75) (layers *.Cu *.Mask)
6 days ago
(net 8 "Net-(F1-Pad2)") (pintype "power_in") (tstamp 8833a204-837c-4874-a347-bdee2154c671))
6 days ago
)
(footprint "circuit:Littelfuse_FuseHolder_FL1_178.6764.0001" (layer "F.Cu")
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6 days ago
(at 116.35 89.6 180)
6 days ago
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(pad "1" thru_hole circle (at -4 0 180) (size 1.5 1.5) (drill 0.75) (layers *.Cu *.Mask)
6 days ago
(net 20 "/5V_5A") (pintype "power_out") (tstamp 7f13857f-975f-45ad-8104-72acd2aaefb8))
6 days ago
(pad "2" thru_hole circle (at 4 0 180) (size 1.5 1.5) (drill 0.75) (layers *.Cu *.Mask)
6 days ago
(net 8 "Net-(F1-Pad2)") (pintype "power_in") (tstamp 8f5c808a-9b59-4503-bba5-a77ce2e766fd))
6 days ago
)
(footprint "circuit:Generic_HeaderSocket_1x04_P5.08mm_Vertical_Open" (layer "F.Cu")
(tedit 5B785047) (tstamp 44597ef0-8540-4558-b023-0a8e08181223)
6 days ago
(at 172.72 58.42 180)
6 days ago
(descr "Generic socket for pluggable terminal block")
(property "Sheetfile" "circuit.kicad_sch")
(property "Sheetname" "")
(path "/43bbb8c2-ccce-4e58-8023-406957fab653")
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6 days ago
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6 days ago
(pad "2" thru_hole oval (at 5.08 0 180) (size 2.08 3.6) (drill 1.4) (layers *.Cu *.Mask)
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(net 15 "Net-(J13-Pad3)") (pinfunction "Clignotant") (pintype "passive") (tstamp 8f690ec6-da32-460e-b0ad-7f216545348a))
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(pad "4" thru_hole oval (at 15.24 0 180) (size 2.08 3.6) (drill 1.4) (layers *.Cu *.Mask)
6 days ago
(net 2 "GND1") (pinfunction "GND") (pintype "power_in") (tstamp b61f82cc-e6c6-49a2-afc2-dc39387b10a7))
6 days ago
(model "${KICAD6_3DMODEL_DIR}/Connector_Phoenix_MSTB.3dshapes/PhoenixContact_MSTBVA_2,5_4-G-5,08_1x04_P5.08mm_Vertical.wrl"
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6 days ago
(footprint "circuit:TerminalBlock_Amphenol_HG0200X0000G_1x02_P5.00mm_45Degree" (layer "F.Cu")
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6 days ago
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